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国家自然科学基金(90407006)

作品数:17 被引量:49H指数:3
相关作者:王志华池保勇姚金科王自强陈弘毅更多>>
相关机构:清华大学更多>>
发文基金:国家自然科学基金国家重点基础研究发展计划国家高技术研究发展计划更多>>
相关领域:电子电信更多>>

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17 条 记 录,以下是 1-10
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A fractional-N frequency synthesizer for WCDMA/Bluetooth/ZigBee applications被引量:2
2009年
A triple-mode fractional-N frequency synthesizer with a noise-filter voltage controlled oscillator(VCO) for WCDMA/Bluetooth/ZigBee applications has been implemented in 0.18-μm RF-CMOS technology.The proposed synthesizer achieves a good phase noise lower than-80 dBc/Hz in band and-115 dBc/Hz @ 1 MHz for the three modes, and only draws 21 mA from a 1.8 V supply.It has a high hardware sharing and a small size, only 1.5 × 1.4 mm2.The system architecture, circuit design, and measured results are also presented.
周春元李国林张春池保勇李冬梅王志华
关键词:MULTI-STANDARDPLLVCO
Automatic IQ Phase Calibration Design in a 2.4GHz Direct Conversion Receiver被引量:1
2006年
An automatic IQ phase calibration method implemented in a 2.4GHz direct conversion receiver is proposed. It uses a delay locked loop (DLL) with a proposed quadrature phase detector to greatly reduce the phase error. The receiver is fabricated in a 0.18μm CMOS process. Measurements show that the IQ phase error can be calibrated within 1°,which satisfies the system requirement.
刘瑞峰李永明陈弘毅王志华
A High Linearity,13bit Pipelined CMOS ADC被引量:2
2008年
A 13bit,pipelined analog-to-digital converter (ADC) designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio (SNDR) and 90. 5 dBc of spurious-free dynamic range (SFDR) for 2.4MHz input at 2.5MS/s. At full speed conversion (5MS/s) and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.
李福乐段静波王志华
关键词:GAIN-BOOSTING
Low Phase Noise Quadrature Oscillators Using New Injection Locked Technique被引量:2
2005年
A low phase noise quadrature oscillator using the new injection locked technique is proposed. The incident signal is directly injected into the common-source connection of the sub-harmonic oscillator. In principle, the phase noise performance of the quadrature output is better than the sub-harmonic oscillator itself. The quadrature oscillator is implemented in a 0. 25μm CMOS process. Measurements show the proposed oscillator could achieve a phase noise of --130dBc/Hz at 1MHz offset from 1. 13GHz carrier while only drawing an 8.0mA current from the 2.5V power supply.
池保勇朱晓雷王自强王志华
关键词:OSCILLATORCMOS
A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications被引量:1
2005年
A 2. 4GHz CMOS monolithic transceiver front-end for IEEE 802. llb wireless LAN applications is presented. The receiver and transmitter are both of superheterodyne structure for good system performance. The frontend consists of five blocks., low noise amplifier,down-converter, up-converter, pre-amplifier, and LO buffer. Their input/output impedance are all on-chip matched to 50 Ω except the down-converter which has open-drain outputs. The transceiver RF front-end has been implemented in a 0. 18μm CMOS process. When the LNA and the down-converter are directly connected, the measured noise figure is 5.2dB, the measured available power gain 12. 5dB, the input l dB compression point --18dBm,and the third-order input intercept point --7dBm. The receiver front-end draws 13.6mA currents from the 1.8V power supply. When the up-converter and pre-amplifier are directly connected, the measured noise figure is 12.4dB, the power gain is 23. 8dB, the output ldB compression point is 1.5dBm, and the third-order output intercept point is 16dBm. The transmitter consumes 27.6mA current from the 1.8V power supply.
池保勇石秉学王志华
关键词:CMOSLNAPREAMPLIFIER
使用三位三阶Δ∑调制器的集成1GHz小数频率合成器被引量:2
2005年
本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μmCMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.
池保勇朱晓雷黄水龙王志华
关键词:△∑调制器频率合成器压控振荡器锁相环
CMOS可变增益放大器设计概述被引量:22
2005年
可变增益放大器是模拟单元电路之一,起着变化增益、调整信号动态范围、稳定信号功率的作用。文章综述了CMOS集成可变增益放大器的研究情况;给出了可变增益放大器的定义、应用、分类和主要指标,描述了多种开环和闭环放大器的结构,分析了相应的增益控制方法及其优缺点;说明了在CMOS工艺下实现放大器增益按指数变化的几种途径。最后,介绍了用于无线数字通信,具有宽带、高线性、低电源电压等高性能可变增益放大器的设计实例。
王自强池保勇王志华
关键词:放大器可变增益放大器可编程增益放大器
L波段数字声广播接收机CMOS集成模拟前端被引量:1
2005年
本文设计了使用CMOS工艺 ,单片集成的L波段数字声广播 (DAB)接收机模拟前端 .接收机前端应用了三种方法来提高镜像抑制度 :低中频双正交weaver结构比一般的同相 /正交 (I/Q)两路下变频结构具有更高的镜像抑制能力 ;镜像抑制低噪声放大器 (LNA)提供了额外的镜像信号抑制 ;具有相位和幅度校正功能的本振驱动器提供了更精确的正交本振信号 .仿真显示接收机前端对镜像信号的抑制超过 6 5dB ,其级联噪声指数为 4dB ,输出三阶交调指数为 2 2dBm .接收机前端使用TSMC 0 .2 5 μmCMOS工艺制作 ,版图核心面积为 9mm2 ,目前正在测试中 .
王自强池保勇林敏韩书光刘璐姚金科王志华
关键词:接收机前端低中频镜像抑制
A 2GHz Low Power Differentially Tuned CMOS Monolithic LC-VCO被引量:1
2006年
A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range (from 1. 8998 to 2. 2335GHz) through a combination of analog and digital tuning techniques (4-bit binary switch-capacitor array). The measured phase noise is - 118.17dBc/Hz at a 1MHz offset from a 2. 158GHz carrier. With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits. The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors. The VCO draws a current of about 2. lmA from a 1.8V power supply and works normally with a 1.5V power supply.
张利池保勇姚金科王志华陈弘毅
关键词:CMOSVCO
CMOS功率放大器在射频识别技术中的应用概述被引量:2
2006年
针对国内外射频识别技术的迅猛发展,结合射频识别技术的应用背景,阐述了读写器中最大的耗能器件—功率放大器的研究现状;指出CMOS工艺应用于功率放大器设计的局限性和可行性;最后,探讨了将CMOS功率放大器应用于射频识别技术的主要研究方向。
高同强池保勇王敬超马长明张春王志华
关键词:功率放大器射频识别技术CMOS工艺
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