This paper present a highly-integrated neurostimulator with an on-chip inductive power-recovery fron- tend and high-voltage stimulus generator. In particular, the power-recovery frontend includes a high-voltage full- wave rectifier （up to 100 V AC input）, high-voltage series regulators （24/5 V outputs） and a linear regulator （1.8/ 3.3 V output） with bandgap voltage reference. With the high voltage output of the series regulator, the proposed neurostimulator could deliver a considerably large current in high electrode-tissue contact impedance. This neu- rostimulator has been fabricated in a CSMC 1 μm 5/40/700 V BCD＇process and the total silicon area including pads is 5.8 mm2. Preliminary tests are successful as the neurostimulator shows good stability under a 13.56 MHz AC supply. Compared to previously reported works, our design has advantages of a wide induced voltage range （26-100 V）, high output voltage （up to 24 V） and high-level integration, which are suitable for implantable neu- rostimulators.
A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorder Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter （SAR ADC）, and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 μS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.
A prototype of hybrid neural recording interface has been developed for extracellular neural recording. It consists of a silicon-based plane microelectrode array and a CMOS low noise neural amplifier chip. The neural amplifier chip is designed and implemented in 0.18 μm N-well CMOS 1P6M technology. The area of the neural preamplifier is only 0.042 mm2 with a gain of 48.3 dB. The input equivalent noise is 4.73 btVrms within pass bands of 4 kHz. To avoid cable tethering for high dense mul- tichannel neural recording interface and make it compact, flip-chip bonding is used to integrate the preamplifier chip and the microelectrode together. The hybrid device measures 3 mm×5.5 mm×330μm, which is convenient for implant or in-vivo neu- ral recording. The hybrid device was testified in in-vivo experiment. Neural signals were recorded from hippocampus region of anesthetized Sprague Dawley rats successfully.
HAN JianQiangZHANG XuPEI WeiHuaGUI QiangLIU MingCHEN HongDa
