Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feedthrough compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.
测量了应力前后 Ga As PHEMT器件电特性的退化 ,指出了 Ga As PHEMT阈值电压的退化由两个原因引起 .栅极下 Al Ga As层深能级的空穴积累可以解释阈值电压漂移中暂时性的、可恢复的那部分 ,积累在栅金属与半导体之间界面层的空穴可以解释阈值电压漂移中永久性的漂移 .空穴积累来源于场助作用下电子的退陷和沟道中碰撞电离产生的空穴向栅极流动时被俘获 .对高场下碰撞电离率的实验曲线进行拟合 ,得到碰撞电离率与器件沟道电场峰值的量化关系 ,可以对 Ga As
研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD)SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的.
