This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed. The optimized LPSR SRAM64K × 32 is used in SoC and the testing method of the LPSR SRAM64K × 32 is also discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies 5. 6mm× 5. 6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K ×32 obtains 17. 301% power savings and the yield of the LPSR SRAM64K × 32s per wafer is improved by 13. 255%.
A compact drain current including the variation of barrier heights and carrier quantization in ultrathin-body and double-gate Schottky barrier MOSFETs （UTBDG SBFETs） is developed. In this model, Schrodinger＇s equation is solved using the triangular potential well approximation. The carrier density thus obtained is included in the space charge density to obtain quantum carrier confinement effects in the modeling of thin-body devices. Due to the quantum effects, the first subband is higher than the conduction band edge, which is equivalent to the band gap widening. Thus, the barrier heights at the source and drain increase and the carrier concentration decreases as the drain current decreases. The drawback of the existing models,which cannot present an accurate prediction of the drain current because they mainly consider the effects of Schottky barrier lowering （SBL） due to image forces,is eliminated. Our research results suggest that for small nonnegative Schottky barrier （SB） heights,even for zero barrier height, the tunneling current also plays a role in the total on-state currents. Verification of the present model was carried out by the device numerical simulator-Silvaco and showed good agreement.
