在时间同步系统中,时间间隔的测量至关重要。提高时间间隔测量的精度,可以让整个定位系统的定位更精确。延迟线内插法是近年来广泛研究和采用的一种时间间隔测量方法。同时内插法结合电子计数器可以扩大测量量程,从而同时达到高精度、大量程的测量需求。本文针对定位系统时间间隔测量的需求,采用全定制芯片实现方式,在0.18 um COMS工艺下,实现了128级延时单元的延时链,仿真单级延时67 ps,实际测试该芯片的测量精度在1 ns以内。
A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （DCOC）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.
