A fully monolithic power amplifier （PA） for multi-mode front end IC integration is presented. The PA is fabricated in an IBM 7WL 0.18 μm SiGe BiCMOS process with all the matching networks integrated on a chip. After load-pull test to find the best power stage size and layout optimization, the measured results show that the PA can obtain a 24 dBm maximum output power at 2.4 GHz, the output 1 dB compression point is 21 dBm at 5 dBm input, and the PAE is 18%. This PA is complete on-chip tested without any bonding wires and on-board matching, targeting fully power module integration in multi-mode system on chip.
Based on our previous work, the influence of annealing conditions on impurity species in in-situ arsenic （As）- doped Hg1-xCdxTe （x ≈ 0.3） grown by molecular beam epitaxy has been systematically investigated by modulated photoluminescence spectra. The results show that （i） the doped-As acting as undesirable shallow/deep levels in asgrown can be optimized under proper annealing conditions and the physical mechanism of the disadvantage of high activation temperature, commonly assumed to be more favourable for As activation, has been discussed as compared with the reports in the As-implanted HgCdTe epilayers （x ≈ 0.39）, （ii） the density of VHg has an evident effect on the determination of bandgap （or composition） of epilayers and the excessive introduction of VHg will lead to a short-wavelength shift of epilayers, and （iii） the VHs prefers forming the VHg-ASHg complex when the inactivated-As （AsHg or related） coexists in a certain density, which makes it difficult to annihilate VHg in As-doped epilayers. As a result, the bandedge electronic structures of epilayers under different conditions have been drawn as a brief guideline for preparing extrinsic p-type epilayers or related devices.
基于0.18μm RF SOI CMOS工艺,提出了一种可广泛应用于无线通信系统中的低插入损耗高隔离度SOI射频开关电路。该电路利用SOI器件的特殊结构(隐埋氧化层BOX,高阻衬底)和特殊SOI器件(FB,BC,BT等),使电路采用的器件较之体硅CMOS器件具有更优的隔离性能,实现了降低插入损耗和增加隔离度的目的。该电路经过模拟仿真,在频率为2.4GHz时,插入损耗和隔离度分别为-1dB和40dB。
