A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise performance.Under a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below 40mW.The measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less.The chip area is only 0.70mm×0.70mm.According to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.
利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率为9.953 28 G b/s长度为223-1伪随机序列的情况下,提取出的时钟的均方根抖动是1.18 ps,峰峰值抖动是8.44 ps。芯片面积为0.5 mm×1 mm,采用-5 V电源供电,功耗约为100 mW。
