A multi layer gridless area router is reported.Based on corner stitching,this router adopts tile expansion to explore path for each net.A heuristic method that penalizes nodes deviating from the destination is devised to accelerate the algorithm.Besides,an enhanced interval tree is used to manage the intermediate data structure.In order to improve the completion rate of routing,a new gridless rip up and rerouting algorithm is proposed.The experimental results indicate that the completion rate is improved after the rip up and reroute process and the speed of this algorithm is satisfactory.
An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate delay estimation.And heuristic method of buffer insertion is presented to reduce delay.The algorithm is tested by industral circuit case.Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.
An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet the delay constraint.A high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look-up table is for buffer delay estimation.The experimental results show that the algorithm can efficiently achieve the trade-offs between number of buffers and delay,and avoid needless power and area cost.The running time is satisfactory.
A cross point assignment algorithm is proposed under consideration of very long nets (LCPA).It is to consider not only the cost of connection between cross points and pins and the exclusive cost among cross points on the boundary of a global routing cell,but also the cost of displacement among cross points of the same net.The experiment results show that the quality and speed in the following detailed routing are improved obviously,especially for very long nets.
Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.
