An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.
To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.
The conventional circuit model of a bit-stream adder based on sigma delta（∑Δ） modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit（IC） of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC＇s 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.
