提出了一种适用于DVB(Digital Video Broadcasting)系统的低复杂度Reed-Solomon解码器结构.在解码器的设计中充分利用了DVB系统提供的高倍率时钟,提高了核心算法模块的计算速度,优化了解码器的流水线结构,有效减小了芯片面积.解码器用SMIC 0.25μm工艺综合后规模为31 000门.
A single-chip DVB-C quadrature amplitude modulation（QAM） demodulator is proposed,which integrates a 3.3V 10bit 40MSPS analog-to-digital converter and a forward error correction decoder. The demodulator chip can support 4-256 QAM with variable bit rate up to 80Mbps. It features a wide carrier offset acquisition range,optimal demodulation algorithm,and small circuit area. The chip is implemented in SMIC 0.25μm 1P5M mixed-signal CMOS technology with a die size of 3.5mm×3. 5mm. The maximum power consumption is 447mW.
