A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tuning techniques （4-bit binary switch-capacitor array）. The measured phase noise is - 118.17dBc/Hz at a 1MHz offset from a 2. 158GHz carrier. With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits. The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors. The VCO draws a current of about 2. lmA from a 1.8V power supply and works normally with a 1.5V power supply.
为保证无线内窥胶囊在电池供电情况下,能实现全消化道检查,提出了一种微型胶囊内的单片低功耗数模混合集成电路的设计。该单片系统主要包括图像采集、图像压缩,存储器和无线收发模块等。数字部分的低功耗设计能比无能量管理策略设计方法要节约36%的功耗,数字电路部分的功能和能量管理策略通过了验证,模拟射频电路部分的主要指标已通过仿真验证,整个数模混合芯片已采用0.18μm的CM O S工艺流片。
We report a low power ASK IF receiver for short-range wireless systems,which includes an AGC loop that compensates the channel attenuation and an ASK detector. A novel current-limited transconductor and feed-forward differential peak detector have been designed to maintain a high compression ratio and fast response for the AGC with lower power consumption. A storage unit with a zero and a feed-forward structure have been introduced into the peak detector to control the damping characteristic of the AGC loop. A rectifier and low-pass filter included in the ASK detector have been integrated into a more compact structure to further lower the power consumption. The simulation results show the feasibility of the proposed technique.
A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.
