A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.
